總 計 畫：百億位元的乙太網路系統晶片設計 子計畫(一)：百億位元乙太網路之傳輸模型及系統架構設計

In the first part of this report, the data deserializer after clock data recovery (CDR) and
the PCS service interface in the receiver of 10G-LX4 Ethernet are presented. We divide the
circuits into two parts: (1) 1: 10 Deserializer. In the deserializer, the serial data (3.125Gb/s) is
deserialized into 10-bit parallel data and the comma word is continuously detected. (2)
Channel Deskew Circuit. This circuit is to align the data among four channels. After
alignment, 32-bit data propagate to the MAC layer via the PCS service interface.
In the second part of this report, the simulation result of including an optical filter to
reduce the fiber dispersion caused by frequency chirp of a direct modulated laser diode
without cooling is presented. With appropriate bandwidth and center frequency, we have
demonstrated that the transmission distance can indeed be extended at data rates up to
10Gbps.