Coverage directed testbench generation for still image CODEC IP's
Date Issued
2005
Date
2005
Author(s)
Lo, Wei-Lung
DOI
en-US
Abstract
Verification has become the bottleneck in the hardware design process, and
one of the hardest verification problems is to verify the correctness of the RTL code.
In this paper, a testbench configuration to obtain high toggle coverage for still
CODEC image IP's is proposed.
In the configuration, an image template composed of key image characteristics, e.g., high
and low spatial frequency components, is proposed as the basic building block of the
testbench.
The parameters of each building block, including the ratio and location of the high/low frequency
components, are determined by simulated annealing.
The proposed testbench is applied to four image CODEC IPs.
Compared to the designer-provided image, commonly used verification images and random images,
the testbench generated by proposed method can achieve the highest toggle coverage.
Subjects
驗證
矽智財
影像處理
verification
testbench
generation
still-image
IP
Type
thesis
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