Leakage-Aware Task Scheduling for Partially Dynamic Reconfigurable FPGAs
Date Issued
2007
Date
2007
Author(s)
Li, Chi-Feng
DOI
en-US
Abstract
As technology advances to 90nm and below, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes imperative for adopting FPGAs in both high performance and low power embedded computing devices. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabric and the prefetch technique. Under the prefetch technique, a task is divided into the reconfiguration component that reconfigures a portion of FPGA for execution and execution component that
performs its functionality. We focus on eliminating leakage waste due to the delay between reconfiguration and execution points. We propose an optimal algorithm based on integer linear programming (ILP) and a two-stage task scheduling algorithm to reduce leakage power without sacrificing performance. In the first stage, we use a performance-driven task scheduler that minimizes the schedule length of an application to generate a feasible placement considering the single reconfiguration
and resource constraints imposed by the target system. In the second stage, we perform post-placement leakage-aware task scheduling to minimize the leakage waste provided that the schedule length obtained by the performance-driven task
scheduler is not increased. Experimental results on real and synthetic designs show that our two-stage algorithm can obtain near-optimal solution with less CPU time compared with the ILP formulation.
Subjects
可程式化邏輯閘陣列
擺置
漏電功耗
排程
效能
FPGA, Placement, Leakage, Scheduling, Performance
Type
thesis
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