A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects
Journal
ASP-DAC 2010, The 15th Asia and South Pacific Design Automation Conference
Pages
651-656
Date Issued
2010-01
Author(s)
Abstract
Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved.
Type
conference paper