5GHz CMOS超低功率射頻前端電路之設計與實現
Design and Implementation of 5-GHz CMOS Ultra-Low-Power Receiver Frontends
Date Issued
2005
Date
2005
Author(s)
Chung, Kuo-Sheng
DOI
en-US
Abstract
With recent advances in the high-frequency characteristics, CMOS has become very
attractive process for the implementation of low-cost wireless communication systems. In
addition to conventional RF systems, low-power and low-voltage applications, such as
RFID and wireless sensor networks, have motivated the development of fully integrated
transceivers using CMOS process. However, the inherently low transconductance and the
required threshold voltage for CMOS process make it extremely difficult to operate
reduced supply voltage and power dissipation. In this thesis, a down-conversion mixer, a
voltage-controlled oscillator (VCO) and a receiver frontend fabricated in 0.18-μm CMOS
are presented to demonstrate the potential of CMOS frontend circuits for low-power and
low-voltage operation.
A novel mixer with stacked complementary transistors and a current bleeding resistor is
proposed for low-voltage application while maintaining reasonable conversion gain. The
5.2-GHz mixer exhibits a conversion gain of 3dB and an IIP3 of -8dBm with a power
dissipation of 792 μW from a 0.6-V supply voltage. As for the proposed VCO topology, the
tail current source of a LC-tank VCO has been eliminated to support ultra-low voltage
operation. 5.8-GHz VCO achieves a tuning range of 8.9% and phase noise of -97dBc/Hz
@ 1MHz. The VCO core consumes 696-μW dc power from a 0.6-V supply voltage. Finally,
by combining the fabricated mixer, VCO with a single stage LNA, the receiver frontend is
designed for the 5-GHz frequency band. Based on the simulation results, the receiver
frontend demonstrates a conversion gain of 15dB and IIP3 of -19dBm. The complete
receiver is operated at a reduced supply voltage of 0.6 V with a power dissipation of
2.3mW.
Subjects
低電壓
低功率
射頻前端接收器
low voltage
low power
receiver frontend
Type
thesis
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