FPGA Implementation of Finite-Difference Time-Domain Algorithm

In this thesis, we use field programmable gate array (FPGA) to implement finite-difference time-domain (FDTD).FDTD is a very powerful algorithm with advantages of minimum assumption and approximation, easy programming,
and ability to analyze time domain variation. It has recently become more and more important in the field of wireless and optoelectronics due to the advancement of computer technology and the development of nanodevices.
However, it requires a huge amount of computation time and memory.Thus, we use FPGA to reduce FDTD computation time.First, FPGA is designed to dedicate to FDTD calculation.Second, pipelining is achieved by means of clock arrangement to reduce computation time of instruction.Third, data access time is reduced by handling recursive calculation and temporary value with high-speed dual-port Block RAM.Finally, parallelism is added into design.Combining the strength above, the computation is greatly speeded up.

The FPGA used is Xilinx Spartan-3 XC3S1500.The numerical representation complies with the IEEE-754 32 bit single-precision floating-point specification.In the FDTD simulation system, parameters and initial values are written via SPI interface,and the results computed by the FPGA are read out for analysis through the VGA interface.

Our results show that the computation speed of 1D FDTD simulation is 30 times faster that of an ordinary 2.01 GHz personal computer when FPGA operated at clock rate of 100 MHz, and 15 times faster for 2D FDTD simulation even without parallelism.Equivalently, it can be hundreds times faster at the same clock rate.Finally, computation speed is doubled approximately by using two parallel computation units for 1D FDTD simulation.