Energy Efficient Nyquist Rate Analog to Digital Converters
Date Issued
2012
Date
2012
Author(s)
Kevin Chen, Hung-Wei
Abstract
Analog to digital converter (ADC) is a bridge between nature signal and digital world. It is an important building block in electronic systems. The applications for ADC are from wireless communications to sensor nodes. Low power, high conversation rate, and high accuracy are the core specifications in the ADC design. In this dissertation, four ADC works are presented and they are used in specified applications. The techniques proposed in this dissertation are used to improve the ADC energy efficiency while maintaining conversion rate and accuracy.
The first work is a 6b 1GS/s ADC for ultra-wide-band (UWB) and data storage systems. Two-channel two-step architecture is proposed to replace conventional high power flash architecture. It dissipates 49mW and obtains 5.44 ENOB in a 0.13-um CMOS. The second work is a 10b 320MS/s ADC for high bandwidth wireless communication. A gain error calibration technique is presented to compensate non-linearity error caused by low gain OPAMPs. It consumes 42mW and achieves 8.71 ENOB in a 90-nm CMOS. The third work is a 12b 10MS/s ADC for low power wireless communication systems. A sub-range concept is adopted into the SAR architecture to reduce the DAC settling time. It dissipates 3mW and obtains 9.62 ENOB in the 0.13-um CMOS. The final work is a 10b 100KS/s ADC for ultra-low power sensor nodes. A charge pump S/H circuit and the DAC output common mode biased at VDD allow ultra-low voltage operation. It consumes 340nW and achieves 8.71 ENOB in the 0.13-um CMOS. The figure of merit of this ADC is 8.4fJ/conversion-step which achieves the lowest by 0.13-um CMOS process in paper reported.
Subjects
Analog to Digital Converter
Two-step ADC
SAR ADC
Pipeline ADC
Low Voltage ADC
Sub-range SAR ADC
Two-channel ADC
SDGs
Type
thesis
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