DR-scan: Dual-rail Asynchronous Scan DfT and ATPG
Journal
IEEE Transactions on Computer Aided Design
Journal Volume
38
Journal Issue
1
Pages
136-148
Date Issued
2019
Author(s)
Shih-An Hsieh
Ying-Hsu Wang
Ting-Yu Shen
Kuan-Yen Huang
Chia-Cheng Pai Tsai-Chieh Chen
James Chien-Mo Li
Abstract
Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits.
Type
journal article