Logic 90 nm n-channel field effect transistor current and speed enhancements through external mechanical package straining
Journal
Japanese Journal of Applied Physics
Journal Volume
47
Journal Issue
4 PART 2
Pages
3127-3129
Date Issued
2008
Author(s)
Liao, W.-S.
Huang, S.-Y.
Tang, M.-C.
Liaw, Y.-G.
Chen, K.-M.
Shih, T.
Tsen, H.-C.
Chung, L.
Abstract
It is demonstrated that the appropriate external mechanical stress applied by the conventional IC chip's package straining can enhance device and circuit performance. A drain current enhancement of 4.9% at saturation is observed for 90-nm-node n-channel metal oxide semiconductor field effect transistor (nMOSFET) under a biaxial tensile strain of 0.096%. The current enhancement is nearly independent of gate width for 90-nm-node logic devices. Moreover, there is a 2.3% speed enhancement for a 90 nm-node logic ring oscillator using a parallel layout under the same biaxial tensile strain of 0.096%.
SDGs
Type
journal article