Formal verification of timed systems: A survey and perspective
Journal
Proceedings of the IEEE
Journal Volume
92
Journal Issue
8
Pages
1283-1305
Date Issued
2004
Author(s)
Abstract
An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation. © 2004 IEEE.
Subjects
Embedded systems; Formal methods; Formal verification; Models; Real-time systems; Specification; Temporal logics; Theory; Tools
Other Subjects
Computational complexity; Computer programming languages; Computers; Embedded systems; Formal logic; Mathematical models; Theory; VLSI circuits; Formal methods; Formal verification; Real-time systems; Specification; Temporal logics; Real time systems
Type
conference paper