Fast neural decoders for some cyclic codes
Journal
International Journal of Electronics
Journal Volume
75
Journal Issue
4
Pages
595-600
Date Issued
1993
Author(s)
Abstract
A number of cyclic and BCH code decoders that have 0(1) time complexity and less hardware complexity than conventional digital decoders are presented. The neural decoder is formulated as a set of parity networks in the first layer followed by a linear perceptron in the second layer, and thus has simple implementation in VLSI technology.
Type
journal article