Performance optimization by wire and buffer sizing under the transmission line model
Journal
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages
192-198
Date Issued
2001-09
Date
2001-09
Author(s)
Abstract
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the transmission line behavior for delay computation. We present in this paper an analytical formula for the delay computation under the transmission line model. Extensive simulations with SPICE show the high fidelity of the formula. Compared with previous works, our model leads to smaller average errors in delay estimation. Based on this formula, we show the property that the minimum delay for a transmission line with reflection occurs when the number of round trips is minimized (i.e., equals one). Besides, we show that the delay of a circuit path is a posynomial function in wire and buffer sizes, implying that a local optimum is equal to the global optimum. Thus, we can apply any efficient search algorithm such as the well-known gradient search procedure to compute the globally optimal solution. Experimental results show that simultaneous wire and buffer sizing is very effective for performance optimization under the transmission line model.
Other Subjects
Computer simulation; Error analysis; Gates (transistor); Interconnection networks; Optimization; Transmission line theory; Delay computations; Buffer storage
Type
journal article
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