A 12Gb/s AC Coupled Chip-to-Chip Receiver
Date Issued
2011
Date
2011
Author(s)
Hung, Shuo-Hong
Abstract
As technology scaling, the frequency of on-chip circuits are much faster, however the speed of off-chip structures are slower. Designing high-speed, lower power and high-density I/O become very important to fill the gap between on-chip and off-chip bandwidth and other problems. Some papers proposed AC coupled interconnect (ACCI) to solve above problem.
This thesis proposed an AC coupled chip-to-chip receiver for high density interconnect. The receiver includes capacitive coupling capacitors, bias circuit, pulse converter, limited amplifier and output buffer. The function of the pulse converter convert a return zero (RZ) pulse into non-return zero (NRZ) data from the transmitted side. The amplitude of the receiver is still small, we design a limiting amplifier to amply. Active peaking technique is applied to enhance the bandwidth of the limited amplifier which is occupied smaller area than on-chip spiral inductor.
In conclusion, the proposed receiver can operate at 12 Gb/s and the power consumption is 19.3 mW with 135-fF on-chip coupling capacitors, which achieves the specification of HDMI1.4a (10.2Gb/s). The chip is fabricated with TSMC 018μm COMS process It also occupies an active area of 0.0512mm^2.
Subjects
ACCI
active peaking
small area
high speed
receiver
Type
thesis
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