CMOS 單晶片分數型鎖相迴路頻率合成器之設計與應用
The Design and Application of CMOS Fully-Integrated PLL-Based Fractional-N Frequency Synthesizers
Date Issued
2007
Date
2007
Author(s)
Yang, Yu-Che
DOI
en-US
Abstract
Conventional integer-N frequency synthesizers suffer from fundamental tradeoffs among frequency step size, loop bandwidth, phase noise, and reference spurs. Since the output frequency is an integer multiple of the input frequency, it is impossible to decouple the ties among these parameters and the performances of the synthesizer are thus limited. To resolve these problems, various kinds of fractional frequency synthesizers have been proposed and because they can generate fractional division ratio, the tradeoffs in integer-N synthesizers can thus be removed. Among these structures, the ΔΣ fractional-N frequency synthesizer, for its lower spurs magnitude and high-pass noise shaping ability, is most often adopted. However, the quantization phase noise and fractional spurs still limit the performance of fractional-N synthesizers.
Quantization induced phase noise results in the noise-bandwidth tradeoff in a ΔΣ fractional-N frequency synthesizer, which substantially reduces the maximum bandwidth and limits the performances of the frequency synthesizer. In this dissertation, a quantization noise suppression technique, which is based on the reduction in the frequency step size of the frequency divider, is proposed. Measurement results show that by using the proposed technique, the quantization phase noise can be lowered by 6 dB. Besides, the experimental results also show that the quantization phase noise is proportional to the quantization level.
In this dissertation we also present a multi-standard fractional-N frequency synthesizer for digital TV tuners. Multi-standard DTV frequency synthesizers have several design challenges, such as wide tuning range, various channel spacing, and low phase noise. To fulfill these requirements, one usually has to use two or three VCOs in a frequency synthesizer. Nevertheless, doing so increases the power consumption and chip area, which is not a satisfactory solution. Our proposed synthesizer makes uses of the fractional-N structure to achieve low in-band phase noise and small channel spacing. On the other hand, only one VCO oscillating at higher frequency and divided down by the band-selecting divider is used to save power consumption and chip area. This synthesizer is design in the TSMC 0.13-um CMOS process and occupies an area of only 0.54 mm2 while consumes a power of only 16.8 mW from a 1.2-V power supply.
In Chapter 8 of this dissertation, a quantization noise pushing technique is presented. This technique increases the operating frequency of the ΔΣ modulator so as to move the quantization noise to a higher frequency and thus it can be further suppressed by the PLL. Meanwhile, the comparison frequency of the PFD will not be increased, so that the PLL loop gain can be kept small and decreases the in-band phase noise. The experimental result show that the in-band phase noise can be lowered by 12 dB while the out-of-band phase noise can be reduced by more than 15 dB compared with the synthesizers having the same PFD comparison frequency.
Subjects
鎖相迴路
頻率合成器
分數型
三角積分調變器
射頻
積體電路
phase-locked loop
frequency synthesizer
delta-sigma
fractional-N
radio-frequency
IC
Type
thesis
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