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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A fast-lock low-power subranging digital delay-locked loop
Details
A fast-lock low-power subranging digital delay-locked loop
Journal
IEICE Transactions on Electronics
Journal Volume
E93-C
Journal Issue
6
Pages
855-860
Date Issued
2010
Author(s)
Chen, H.-S.
Lin, J.-C.
HSIN-SHU CHEN
DOI
10.1587/transele.E93.C.855
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-77952968773&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/357877
SDGs
[SDGs]SDG7
Type
journal article
