Triple-mode MAP/VA timing analysis for unified convolutional/turbo decoder design
Resource
Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Pages
280-285
Date Issued
2004
Date
2004
Author(s)
DOI
N/A
Abstract
To satisfy the advanced FEC standard that performs both convolutional coding and turbo coding, a unified convolutional/turbo decoder is needed. The timing of both Viterbi and MAP algorithms are analyzed. We introduce three techniques, including interleaving, pointer, and parallel schemes, which can be used in timing charts to reduce memory or increase throughput. In recent works, several timing charts of VA or MAP have been presented, but there is no combined timing analysis of both algorithms. We propose two types of triple-mode MAP/VA timing charts by complementing the idle times of each other.
Type
conference paper
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