BIST Design for Jitter Injection of High Speed Transceivers
Date Issued
2005
Date
2005
Author(s)
Li, Kong-Ping
DOI
en-US
Abstract
For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high-speed I/O and bus standards. Typically, jitter specifications are tested by external ATE (automatic test equipment), but the elevating data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement methods. In this work, we propose an on-chip jitter injection technique for receiver jitter tolerance testing. With the target clock rate of 1GHz, this technique can inject 240 ps peak-to-peak jitter with 8 ps resolution
Subjects
抖動
容忍度測試
內建自我測試
jitter injection
jitter tolerance testing
BIST
Type
thesis
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ntu-94-R92943068-1.pdf
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