Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS
Journal
2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020
Date Issued
2020
Author(s)
Chiueh, H.
Yang, C.-H.
Wen, C.H.-P.
Yang, C.-G.
Chien, P.-H.
Hung, C.-Y.
Chen, Y.-J.
Wang, Y.-P.
Chiu, C.-F.
Lin, J.
Abstract
An integrated design framework is proposed to automate radiation-harden (rad-hard) VLSI systems in a standard CMOS technology. TMR, DICE, SERL, ELT, and ECC techniques are integrated across architecture, circuit, and layout levels. Performance of the rad-hard cells were evaluated in 0.18μm CMOS. A rad-hard RISC processor targeting for an inclination micro-satellite on a 720km orbit was realized in 90nm CMOS. The chip was tested by applying heavy ions with corresponding radiation dose. The rad-hard RISC processor functions under all the test conditions (LET 2 /mg), validating the effectiveness of the methodology.
SDGs
Type
conference paper