High Speed, Low Power Pipeline Analog-to-Digital Converter
Date Issued
2016
Date
2016
Author(s)
Tseng, Chien-Jian
Abstract
Opamp is a critical and power-hungry block in high performance pipeline ADC design. Unfortunately, opamp design is getting challenging in advanced deep submicron process. The techniques proposed in the dissertation aim to ease opamp design effort or simply remove opamp usage in pipeline ADC design. The first and second designs employ incomplete settling technique to realized high speed ( > GS/s ) pipeline ADC design. Two novel design concepts, sampling point calibration and sub-radix conversion, are adopted to calibrate stage gain error. Thus, low gain and low bandwidth opamps can be used in pipeline ADC design to save power consumption. The third design extends the usage of capacitor sharing technique, not only between the 1st and 2nd MDACs but also between the 2nd and the 3rd MDACs. By reducing the effective capacitance loading at opamp output node, the bandwidth requirement of the opamp can be loosen. The final design tries to get rid of opamp usage in the pipeline ADC design. The MDAC function, i.e. subtraction and amplification, can be realized by merely constant charging current source, capacitors and comparators. In addition, processing signal in time domain instead of in voltage domain takes advantage of increasing timing resolution in advanced process and thus fits the process trend.
Subjects
pipeline ADC
power efficiency
incomplete settling
capacitor sharing
time domain
Type
thesis