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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
Details
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
Journal
Symposium on VLSI Circuits
Pages
140-143
Date Issued
2005-06
Author(s)
Jri Lee
Shanghann Wu
JRI LEE
DOI
10.1109/VLSIC.2005.1469352
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/318061
Type
conference paper
