Fault-tolerant serial-parallel multiplier

The paper presents a novel fault-tolerant circuit design using a time-redundancy method for a serial-parallel multiplier, which is useful in DSP applications with serial data transmission. It utilises the RECO (Recomputing with Circularly shifted Operands) technique to detect errors concurrently. A simple OR-gate based circuit is used as the location table to identify faulty bit-slice pairs. The reconfiguration technique is then introduced to bypass the potential faulty bit-slices. This design can have the maximum detectable error region (≅n/2 bits), without appending extra computing elements. The latency from error detection to location is only about two clock cycles, i.e. almost real-time detecting can be achieved. Pipelined timing for two computations is illustrated. The analyses of performance and complexity are described. The results show that this is an efficient design methodology for fault-tolerant multiplication with serial data.