A Low Branch Penalty Processor Supporting Most MIPS Instructions in 0.18um CMOS Technology
Date Issued
2005
Date
2005
Author(s)
Chang, Hung-Chi
DOI
en-US
Abstract
Since the first computer is invented, we are seeking for ways to raise the performance of processors. But the penalty caused by branch instruction is still a problem. Therefore, this thesis mainly describes the implementation of a low branch penalty processor.
The structure we used is basically based on the basic and classic five-stage processor that would be introduced along with its five stages. We separate this structure into two parts: functional blocks, which are the blocks that responsible for the operations in each stage, and the control blocks, which are in charge of the control of the whole design so that the execution flow could work correctly. Besides, the three kinds of hazards (structural hazard, data hazard, and branch hazard) and the method to solve them are also referred. The branch predictor and branch target buffer are also presented.
We took the cell-based design flow as our implementation way. We also show the main point of this cell-based design flow, the way we transform a design into a chip. And then we present the simulation results of the design.
UMC 0.18um 1p6m CMOS technology is used to implement this chip. At last we show the measurement result. This chip can work up to 65MHz with its area of
1765.74(um) x 1652.32(um) and support 37 instruction sets.
Subjects
分支
預測
處理器
branch
prediction
MIPS
processor
0.18um
Type
thesis
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