A Wave Pipeline-Based Jitter Generation Technique for High-Speed Transceiver Design-for-Test Applications
Date Issued
2006
Date
2006
Author(s)
Chang, Shing-Wei
DOI
en-US
Abstract
For modern high speed communication devices, jitter has been an important factor of the achievable data transmission quality. With the growing demand on data bandwidth, meeting the jitter specification is crucial for high speed I/O and bus standards. Typically, jitter specifications are tested by external Automatic Test Equipment (ATE), but the growing data rate makes it difficult, if possible at all, for the ATE to catch up with the performance requirement. Most of the recent works concentrate on jitter measurement. In this thesis, a low-cost on-chip sinusoidal jitter injection technique for system level Built-In Self-Test (BIST) applications is proposed. Simulation results are demonstrated to validate the proposed technique.
Subjects
抖動
抖動產生技術
jitter
design-for-test
Type
thesis
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