Secured IEEE 1500 Test Wrapper for Embedded IP Cores
Date Issued
2008
Date
2008
Author(s)
Chiu, Geng-Ming
Abstract
This thesis presents a new secure test wrapper (STW) design for preventing scan-based attack. The technique provides a secure mechanism to protect primary inputs and scan in/out of internal scan chains in IP core. The secure architecture allows only authorized user to execute all test operation by using secure controller to verify whether test pattern is identical to test wrapper key. The test wrapper key is generated by linear-feedback shift register (LFSR) that is constructed from secure wrapper boundary cell. Experimental results on AES show that STW provides very high security (2256) for a small area overhead (approximately 5%). The architecture is compatible to IEEE 1500 standard and there is no need to modify the embedded IP core in System on Chip (SOC). An automatic compiler and validation tool for secure test wrapper is implemented. The user interface platform that includes compiler and validation tool of secure test wrapper and standard test wrapper is also implemented.
Subjects
IP
SoC
scan-based DFT
side-channel attack
IEEE 1500
test wrapper
security
Type
thesis
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ntu-97-R94943148-1.pdf
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