PAC Duo SoC performance analysis with ESL design methodology
Journal
ASICON 2009 - 8th IEEE International Conference on ASIC
Pages
399-402
Date Issued
2009
Author(s)
Chuang, I.-Y.
Chang, C.-W.
Fan, T.-Y.
Yeh, J.-C.
Ji, K.-M.
Ma, J.-L.
Wu, A.-Y.
Lin, S.-Y.
Abstract
PAC Duo system on chip (SoC) is a high performance and low power multimedia tri-core SoC designed at SoC Technology Center (STC) of Industrial Technology and Research Institute (ITRI). We are facing a situation of continuous increasing of design complexity, when we integrate more components and try to evaluate the system performance or do further architecture exploration. In this paper, we present a system-level virtual platform and simulation environment for performance profiling and evaluation based on electronic system-level (ESL) design methodology. Through the fine-tuning of functionality, timing, and simulation speed, the resulted virtual platform achieves a high accuracy with a less than 10% of the cycle count error against RTL simulation with an 80~150 times simulation performance improvement. With this methodology, the system function evaluation and performance profiling can be easily realized. We also show the experimental results for various multimedia applications compared with RTL simulation and further demonstrate how the virtual platform successfully predicts the real chip performance of the evaluation board.
SDGs
Type
conference paper