MR: A New Framework for Multilevel Full-Chip Routing

In this paper, we propose a novel framework for multilevel
full-chip routing considering both routabilityand performance called MR.
The two-stage multilevel framework consists of coarsening, followed byuncoarsening.
Unlike the previous multilevel routing, MR integrates global
routing, detailed routing, and resource estimation, together at each level
of the framework, leading to more accurate routing resource estimation
during coarsening and thus facilitating the solution refinement during uncoarsening.
Further, the exact routing information obtained at each level
makesMR more flexible in dealing with various routing objectives (such as
crosstalk, power, etc.). Experimental results show that MR obtains significantlybetter
routing solutions than previous works. For example, for a set
of 11 commonlyused benchmark circuits,MRachieves 100% routing completion
for all circuits, while the previous multilevel routing, the three-level
routing, and the hierarchical routing can complete routing for only2, 0, 2
circuits, respectively. In particular, the number of routing layers used by
MR is even smaller.We also have performed experiments on timing-driven
routing. The results are also verypr omising.