Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
Resource
IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 54 (2): 591-602 MAR 2005
Journal
IEEE Transactions on Signal Processing
Journal Volume
53
Journal Issue
4
Pages
1575 - 1586
Date Issued
2005-04
Date
2005-04
Author(s)
DOI
246246/200611150121834
Abstract
In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) architectures are classified into three categories: convolution-based, lifting-based, and B-spline-based. They are discussed in terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues. The 2-D DWT architectures are categorized and analyzed by different external memory scan methods. The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology and working frequency, instead of the required memory size only. Besides the analysis, the B-spline-based IDWT architecture and the overlapped stripe-based scan method are also proposed. Last, we propose a flexible and efficient architecture for a one-level 2-D DWT that exploits many advantages of the presented analysis. © 2005 IEEE.
Subjects
code channel assignment
dynamic adjustment
orthogonal variable spreading factor (OVSF)
Universal Mobile Telecommunications System (UMTS)
wide-band code-division multiple-access (WCDMA)
Publisher
Taipei:National Taiwan University Dept Comp Sci Informat Engn
Type
journal article
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