A Logic Simulator for Timing and Power Analysis

最近幾年來，功率消耗是一項很重要的議題，並且工程師在設計IC時，必頇詳加考慮的一項因數。雖然HSPICE在於估計功率消耗方面，有相當不錯的準確度，然而，在於Circuit-level下模擬所消耗的時間，卻是非常可觀，近來比較複雜的電路設計，往往無法在HSPICE平台上模擬。而一般常用的模擬軟體在於Gate-level下模擬，雖然沒有消耗那麼多的模擬時間，卻往往無法得到所需要的準確度。 我們提出了一個模擬的方法，兼具了兩項的優點，不但可以得到準確的結果，而且可以模擬時間比HSPICE快。我們基於Event Driven模擬器之上，先於Circuit-level下模擬每個邏輯閘的運作狀況，並且紀錄許多參數，以獲得較準確的模擬結果，之後在於速度比較快的Gate-level下模擬整個電路，進而分析整個電路的功率消耗以及時序。我們用平面方程式為模型模擬邏輯閘的延遲時間以及功率消耗，並且我們也提出模型模擬一些被認為是定數的參數，例如負載電容量等。 我們的模擬結果，比HPICE快上約一千倍，平均誤差卻只有六％左右。

In recent years, power consumption has become an important issue that engineers must take into account. Although circuit-level simulators like HSPICE are capable of accurate power consumption estimation, the long simulation time makes them impractical for large designs. Gate-level simulators, on the other hand, are much faster, but the resulting inaccuracy is often unacceptable. In this thesis, we propose a simulator that combines the advantages of the gate and circuit-level simulators — it extends the capability of an event-driven gate-level simulator to obtain power estimation accuracy comparable to that of HSPICE. To achieve this goal, HSPICE is utilized to construct a comprehensive timing model for each logic gate. Using these timing models, accuracy in timing and glitch estimation is much improved. In the past, many logic gate timing models were proposed; however, most of them were over-simplified or fail to consider all the timing related factors or the interactions among the factors. In our simulator, we use a linear model for the delay and the power consumption of each logic gate. The linear model also considers the variable cut value of inertial model and the load capacitance. The simulator has been implemented. Compared to HSPICE, our simulator is about three orders faster, while the simulation results are within 6% of HSPICE.