Fabrication and Characterization of Ge and GeSn MISCAPs
Date Issued
2015
Date
2015
Author(s)
Lin, Tzu-Yao
Abstract
Recently, semiconductor industry technology has followed the path of scaling trend based on Moore’s Law. But conventional planar Si MOSFETs is approaching its fundamental scaling limits. For the continuation of the scaling trend, high mobility materials have been comprehensively investigated as channel material for replacing Si, Ge or GeSn are candidate materials due to its high intrinsic carrier mobility. In this thesis, the fabrication and electrical characterization of germanium (Ge) and germanium-tin alloy (GeSn) Metal-Insulator-Semiconductor Capacitances (MISCAPs) are investigated. In the first of this thesis, rapid thermal oxidation (RTO) is used as an effective way to growth GeO2 interfacial layer to passivate Ge channel and Al2O3 as high-k layer is deposited by atomic-layer-deposition (ALD). The CV characterizations of Ge MISCAPs and the interface trap density extracted by low-temperature conductance method are measured. The MISCAPs with AlGeO interfacial layer has lower interface trap density (Dit) (~10^11cm-2eV-1) than that with GeO2 IL(~10^12cm-2eV-1). The MISCAPs with good quality AlGeO interfacial layer and replaceable work function metal is realized by wet etching of Al film deposited on Al2O3. In the second part of the thesis, GeSn MISCAPs is fabricated with AlGeO interfacial layer. The highest process temperature is limited at 350oC due to the thermal budget of metastable GeSn alloy, which is figured out by the EDX, AFM and XRD of GeSn MISCAPs with different growth temperature. The reliability of AlGeO interfacial layer is analyzed by measuring the hysteresis of C-V characteristic with different constant voltage stress times. The hysteresis of AlGeO (218mV) is lower than GeO2 (297mV) due to the lower border trap density in AlGeO layer. The Hysteresis and flat-band shift of AlGeO can be improved by forming gas annealing (FGA). In the last of this thesis, low-EOT MISCAPs with TiN/ZrO2/Al2O3/Ge gate stack is fabricated with EOT of 0.8nm and Dit of about 10^12cm-2eV-1. The gate stack is used on junctionless Ge gate-all-around FETs with drive current of 828μA/μm. The tensile strain of Ge channel is 0.25% simulated by ANSYS.
Subjects
Ge
GeSn
MISCAPs
AlGeO
interface trap density
hysteresis
strain
Type
thesis