A 3.2GHz digital phase-locked loop with background supply-noise cancellation

Journal

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Journal Volume

59

Pages

332-333

Date Issued

2016

Author(s)

Yeh, C.-W.

Hsieh, C.-E.

DOI

10.1109/ISSCC.2016.7418042

URI

https://scholars.lib.ntu.edu.tw/handle/123456789/499864

URL

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84962844424&doi=10.1109%2fISSCC.2016.7418042&partnerID=40&md5=5ce336fe2310e91d11806ba6f36e6c55

SDGs

[SDGs]SDG7

Type

conference paper