A 1.5GHz phase-locked loop with leakage current suppression in 65nm CMOS
Journal
IET Circuits, Devices & Systems
Journal Volume
3
Journal Issue
6
Pages
350-358
Date Issued
2009-12
Author(s)
Jung-Yu Chang
Abstract
In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4×0.5 mm2. With the leakage suppression circuit, the peak-to-peak jitter and the rms jitter are 43 and 5.36 ps, respectively. The power is 17 mW for a 1.2 V supply.
SDGs
Type
journal article