Rapid IP design of variable-length cached-FFT processor for OFDM-based communication systems
Journal
2006 IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS
Pages
62-65
Date Issued
2006
Author(s)
Abstract
Fast Fourier Transform (FFT) and Inverse FFT (IFFT) are adopted as the demodulation/modulation kernels in OFDM systems. The lengths of FFT/IFFT operations may vary in different applications of OFDM systems. Moreover, due to the trend of system-on-chip (SOC), rapid prototyping and intelligent soft IP designs are important design methodologies. In this paper, we design and implement a variable-length FFT processor to cover different applications of OFDM systems. We propose an efficient design flow which makes re-designing an FFT processor rapid and easy. We adopt cached-memory structure in the FFT processor for low-power consumption issue. Besides, we employ block-floating-point (BFP) arithmetic to acquire high signal to quantization noise ratio (SQNR). Finally, we implement this processor with TSMC0.18μm 1P6M CMOS technology. The simulation results show that the chip can perform 64~2048-point FFT operations at 75 MHz which meet the speed requirements of most OFDM standards such as WLAN, ADSL, VDSL (256~2048), DAB, and DVB (2k mode).
SDGs
Type
conference paper