A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
Resource
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Journal
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Pages
-
Date Issued
2000-08
Date
2000-08
Author(s)
Wang, Bo-Ting
Kuo, J.B.
DOI
N/A
Abstract
Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.
SDGs
Type
journal article
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