A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique

Resource

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Journal

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Pages

-

Date Issued

2000-08

Date

2000-08

Author(s)

Wang, Bo-Ting

Kuo, J.B.

DOI

DOI

N/A

URI

SDGs

[SDGs]SDG7

Type

journal article

File(s)

Name

00952851.pdf

Size

309.56 KB

Format

Adobe PDF

Checksum

(MD5):daeef4a28e4efb9b2f3cbf7878a8d6f1