A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols
Journal
2015 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages
834-837
Date Issued
2015
Author(s)
Abstract
In this paper, we present the implementation of a multi-mode crypto-coprocessor, which can support three different public-key cryptography (PKC) engines (NTRU, TTS, Pairing) used in post-quantum and identity-based cryptosystems. The PKC-based security protocols are more energy-efficient because they usually require less communication overhead than symmetric-key-based counterparts. In this work, we propose the first-of-its-kind tri-mode PKC coprocessor for secured data transmission in Internet-of-Things (IoT) systems. For the purpose of low energy consumption, the crypto-coprocessor incorporates three design features, including 1) specialized instruction set for the multi-mode cryptosystems, 2) a highly parallel arithmetic unit for cryptographic kernel operations, and 3) a smart scheduling unit with intelligent control mechanism. By utilizing the parallel arithmetic unit, the proposed crypto-coprocessor can achieve about 50% speed up. Meanwhile, the smart scheduling unit can save up to 18% of the total latency. The crypto-coprocessor was implemented with AHB interface in TSMC 90nm CMOS technology, and the die size is only 1.96 mm2. Furthermore, our chip is integrated with an ARM-based system-on-chip (SoC) platform for functional verification. © 2015 IEEE.
Subjects
crypto-coprocessor; IoT; Public-key cryptography; SoC
SDGs
Other Subjects
Coprocessor; Energy efficiency; Energy utilization; Hardware security; Network security; Programmable logic controllers; Public key cryptography; Scheduling; System-on-chip; ARM-based systems; Communication overheads; Crypto coprocessor; Functional verification; Internet of Things (IOT); Low energy consumption; Public Key Cryptography (PKC); Security protocols; Internet of things
Type
conference paper