Performance analysis and architecture evaluation of MPEG-4 video codec system
Resource
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Journal
Proceedings - IEEE International Symposium on Circuits and Systems
Journal Volume
2
Pages
II-449-II-452
Date Issued
2000-05
Date
2000-05
Author(s)
DOI
N/A
Abstract
This paper presents various analyses of computational behavior, namely the number of datapath operations and memory access, on the core profile level 2 (CPL2) of MPEG-4 Video standard. These analyzed data exploit the load distribution and mode selection of the video system. The exploration of data-flow behavior and its derived computation of MPGE-4 video processing algorithms will then drive through an efficient architecture design.
Event(s)
Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000
Other Subjects
Algorithms; Computational complexity; Computer architecture; Electric network analysis; Electric network synthesis; Integrated circuit layout; Standards; Video signal processing; Motion picture experts group (MPEG) standards; Video processing algorithms; Digital integrated circuits
Type
conference paper
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