A Power-Aware SWDR Cell for Reducing Cache Write Power
Journal
2003 International Symposium on Low Power Electronics and Design
Pages
14-17
Date Issued
2003-08
Author(s)
Abstract
Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%∼92% reduction in average cache write power dissipated in bitlines.
SDGs
Type
conference paper