Design and Implementation of Broadband Amplifiers for Optical Communication System

The increasing popularity of internet and multimedia communication (digital TV) services has motivated the development of high-speed optical communication system. Commercial STM-64 (OC-192) operating near 10Gb/s and STM-256 (OC-768) operating near 40Gb/s are the main streams today. In recent years, the deep submicron CMOS technology has competitive high-frequency characteristics with high-speed Ⅲ-Ⅴ devices and is gradually used in high-speed circuits. The lower cost and higher level of integration make it more attractive than high-cost III-V technology for commercial use. In this thesis, a 10-Gb/s tunable transimpedance amplifier (TIA) and a 45.6-GHz matrix distributed amplifier are implemented in a standard 0.18-μm CMOS process.
The tunable TIA incorporates a regulated cascode (RGC) input buffer, shunt-peaking technique, voltage-current feedback topology and the applications of variable feedback and load resistors to achieve a 45~52-dBΩ tuning range of transimpedance gain and a 7~10-GHz tuning range of bandwidth at a 2.2-V supply voltage. Total power consumption including output buffer is 32 mW. The whole chip size is 0.83 x 0.66 mm2.
The novel matrix distributed amplifier employs a 2x4 matrix architecture. The proposed circuit adopts interleaving-central-line architecture and cascode gain stages for gain and bandwidth enhancement. Optimized CPW is used to implement the required inductors. With a power consumption of 497mW, a gain of 6.7 dB and a 3-dB bandwidth of 45.6 GHz are measured. The whole die size is 1.8x1.05 mm2.