A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop
Resource
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Journal
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Pages
-
Date Issued
2001-05
Date
2001-05
Author(s)
Chang, Ching-Chi
Lin, Chien-Chih
Shiue, Muh-Tian
Wang, Chorng-Kuang
DOI
N/A
Abstract
This paper proposes a two-fold carrier recovery loop that possesses /spl plusmn/25000-ppm pull-in range and 7-ms acquisition time for 64-QAM blind adaptive system. The carrier recovery system contains a prior wide-band loop to acquire a coarse carrier frequency and a posterior narrow-band loop to achieve -82 dBc jitter suppression. It can be applied to a 4.035-MHz low-IF cable modem system with the /spl plusmn/100-kHz frequency offset tolerance requirement. The two-fold carrier recovery loop operates in consecutive three stages, which are Costas carrier phase estimation, DDML carrier phase estimation, and DD-MMSE carrier phase estimation. The proposed architecture is hardware efficient since the three-staged operation shares most of the circuit functions.
SDGs
Type
journal article
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