Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry
Journal
Digest of Technical Papers - Symposium on VLSI Technology
Journal Volume
2020-June
Date Issued
2020
Author(s)
Abstract
An interpretable neural network (NN) is used to model the self-heating (SH) in complex FinFET circuits. The NN training/testing datasets from 3 -stage to 37 -stage chain circuits in folded layout composed of inverter (INV)/NAND/NOR are simulated by our distributed RthCth SPICE model [1], [2]. The interfacial thermal resistance [3], boundary scattering [4], alloy scattering [5], and layout dependence are considered. The NN interpretation by feature importance analysis is consistent with the thermal physics. Stage# is the most important feature of the NN prediction. Both via2 bundle positions and via2 numbers (via2#) are effective to reduce SH. As compared to SPICE, NN prediction in 37 -stage INV chain computes 3\106X faster with accuracy loss < 1°C. The high computation efficiency and high precision make NN feasible to predict chain circuits up to 40 stages, which cannot be simulated by SPICE due to long computation time. ? 2020 IEEE.
Subjects
FinFET; Forecasting; SPICE; Timing circuits; VLSI circuits; Boundary scattering; Computation time; High computation efficiency; Importance analysis; Important features; Interfacial thermal resistance; Layout dependences; Neural network (nn); Neural networks
SDGs
Type
conference paper