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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
Coarse Grain Parallelization of H.264 Video Decoder and Memory Bottleneck in Multi-Core Architectures
Details
Coarse Grain Parallelization of H.264 Video Decoder and Memory Bottleneck in Multi-Core Architectures
Resource
International Journal of Computer Theory and Engineering, 3(3), 375-381
Journal
International Journal of Computer Theory and Engineering
Pages
375-381
Date Issued
2011
Date
2011
Author(s)
G rhanl, Ahmet
Chen, Charlie Chung-Ping
Hung, Shih-Hao
DOI
10.7763/IJCTE.2011.V3.335
URI
http://ntur.lib.ntu.edu.tw//handle/246246/244502
Type
journal article
File(s)
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07.pdf
Size
23.16 KB
Format
Adobe PDF
Checksum
(MD5):75c8d698e471e3dd4acfb0a89a715ac6
