A Parallelized Decoder of H.264 Scalable Extension for Digital TV
Date Issued
2007
Date
2007
Author(s)
Su, Wei-Kai
DOI
en-US
Abstract
A gracefully scalable video codec which has being an active research topic for 20 years comes into a great deal of maturity. The tradeoff between scalability and coding efficiency has been well-compromised as spatial, temporal, and SNR scalabilities were combined flexibly, with 1dB PSNR degradation as to the single layer approach. Furthermore, the codec’s complexity is taken into consideration all the time.
After two years’ efforts by the Joint Video Team of the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, the Scalable Extension of the H.264/MPEG-4 AVC Video Coding Standard will be finalized in 2007. Accompanying H.264/MPEG-4 AVC of tomorrow’s star and the popularization of Digital TV, we present a scenario ranging from DVB-H(QVGA) to DVB-S2(HD1080) for the application of Digital TV, so as to unify the bit-streams which were prepared respectively and make them even more robust and flexible. Thanks to the advances of hardware, we implemented a more efficient decoder using SIMD instructions and Multi-Core architectures provided by the hardware to parallelize and optimize its implementation.
In the thesis, we firstly introduce Digital TV, H.264/MPEG-4 AVC, and survey the scalable extension of H.264/MPEG-4 AVC, and then describe the techniques we used to parallelize the decoder and the algorithms we designed to make use of these techniques. After that, the experimental results will be given. Finally we conclude this thesis and list the possible directions of our future works.
Subjects
可調式視訊編碼
Scalable Video Coding
Type
thesis
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