Analytical Placement for Modern Mixed-Size Circuit Designs
Date Issued
2012
Date
2012
Author(s)
Hsu, Meng-Kai
Abstract
With the advance of process technology, billions of transistors (or millions of standard cells) can be integrated into a single chip. To facilitate the design complexity, pre-designed macros are often reused, such as embedded memories, analog blocks, intellectual property (IP) modules, etc. Moreover, the three-dimensional integrated circuit (3D IC) technology also emerged to overcome the challenges in interconnect and integration complexity in modern circuit designs. While pre-designed macros usually have areas much larger than those of standard cells, through-silicon vias (TSVs) required for transmitting signals among different dies for the 3D IC technology also occupy more significant silicon areas than standard cells. As a result, a modern circuit design may contain a large number of big blocks and standard cells with various sizes. The great difference between big blocks and small standard cells has incurred significant challenges to modern mixed-size placement. Especially, since pre-designed macros or TSVs usually occupy several metal layers by themselves, these big blocks also bring up significant challenges to circuit routability. Therefore, it is of particular importance to develop effective placement techniques considering the critical issues in modern mixed-size circuit designs including macro placement, routability, and 3D IC integration.
In this dissertation, we propose several novel placement algorithms to consider the aforementioned critical issues. The dissertation first starts with our analytical placement basics which are based on a novel stable weighted-average wirelength model and a new multi-layer sigmoid potential model. Then, we present a unified analytical global placement algorithm based on a novel rotation force to resolve the intrinsic limitations with macro handling for analytical placement. To cope with the significant mismatch between existing wirelength models and the congestion objective in placement, and the macro porosity problem (several metal layers are usually occupied by big macros), we present a novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs by introducing a novel sigmoid function based overflow optimization method and a new net congestion optimization method for analytical placement. For the emerging 3D IC technology, we propose a 3D IC analytical placement algorithm which considers the sizes of TSVs and the physical positions for TSV insertion during placement. Experimental results show the effectiveness and efficiency of our proposed algorithms.
Subjects
Physical Design
Placement
Macro Placement
Routability
3D ICs
Type
thesis
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