Schottky barrier MOSFET process and poly III-V gate device
Date Issued
2006
Date
2006
Author(s)
Wu, Hsien-Ta
DOI
en-US
Abstract
In this work, we focused on how to fabricate a schottky barrier source/drain (S/D) on Si/Ge/Si heterojunction substrate transistor by one mask process. Tantalum covered with Platinum would not be etched by BOE, so it is used to be the gate metal. Metal S/D SB device has some properties including low parasitic S/D resistance, low-temperature processing for S/D formation and atomically abrupt junctions formed at the silicide-silicon interface. In this experiment, the S/D of the transistor were made with platinum on n-type substrate schottky contact. In the characteristics of SB MOSFET, the device with Si/Ge/Si heterojunction substrate has larger leakage current than silicon substrate device. Then, the series resistance effect is serious on each SB MOSFET with one mask process. The schottky diodes with Si, Ge, and Si/Ge/Si (epi-Ge) substrate were also discussed. The schottky barrier diode with epi-Ge substrate has special electronic properties among them. The current-voltage and capacitance-voltage characteristic curves show that energy well in valance band which is due to different band gap of heterojunctions would confine holes at reverse bias, but it would not occur on PtSi and PtGe schottky diodes. Besides, using polycrystalline III-V materials which has different band gap with polycrystalline silicon controls threshold voltage of MOSFET. Finally, we concentrated on the characteristics of MOS capacitor with poly-InAs gate. The work function of poly-InAs did not match the theoretical value in this experiment, but it still could be tuned by changing the dopant elements. Interface trap density between silicon dioxide and silicon increased during growth of poly-InAs.
Subjects
蕭基場效電晶體
三五族
Schottky barrier
poly III-V
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-95-R93943144-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):307db04f77c51ecc5e34b43b6211d817