Algorithm and VLSI Architecture of Unified FEC Decoder Designs
Date Issued
2007
Date
2007
Author(s)
Li, Fan-Min
DOI
en-US
Abstract
To satisfy the advanced Forward-Error-Correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a reconfigurable FEC decoder is needed. Moreover, to reduce the power and latency of the iterative Turbo decoding, an Early Termination (ET) mechanism, in which the FEC decoder can stop according to the channel environment, is needed. In this literature, we propose a unified FEC decoder that contains the features of the dynamic computation and reconfigurable function.
Although many stopping methods of iterative decoding have been discussed in the literatures extensively, many of them only focus on the solvable decoding (information is enough for successful decoding). In this literature, we discuss the limitation of the decoding ability based on the extrinsic information transform (EXIT) chart. Then, we propose a new information measurement by using cross correlation to predict the decoding threshold. Moreover, we propose two early termination (ET) schemes (ET-I and ET-II) based on the predicted decoding threshold. The iterative decoding can stop in either high-SNR situations where the decoded bits are highly reliable (solvable decoding), or low-SNR situations where the decoder already has no capability to decode (unsolvable decoding). The simulation results show that the reduced iterations due to the ET-I scheme almost will not affect the BER performance, and the ones due to the ET-II scheme can still satisfy the requirement of the specification.
For the reconfigurable design, we first systematically analyze the timing charts of both the Viterbi algorithm and the MAP algorithm. Then, three techniques, including Distribution, Pointer, and Parallel schemes, are introduced. Furthermore, we propose a tile-based methodology to analyze the key features of timing charts. On the basis of the timing analysis, we develop a VA/MAP timing chart that has three modes (VA mode, MAP mode, and concurrent VA/MAP mode) by complementing the idle time of both Viterbi and MAP decoding procedures. Then, we construct a triple-mode FEC kernel. By integrating the FEC kernel with different size of memory, we can construct a types of FEC decoders for different application scenarios, such as 1) stand-alone Convolutional decoder (VA mode), 2) stand-alone Turbo decoder (MAP mode), 3) dual-mode Convolutional/Turbo decoder (VA mode and MAP mode), and 4) triple-mode Convolutional/Turbo decoder (VA mode, MAP mode, and concurrent VA/MAP mode). Finally, a prototyping FEC kernel processor that is compliant to 3GPP standard is verified in TSMC 0.18-μm CMOS process.
Subjects
前向錯誤更正碼
渦輪碼
迴旋碼
疊代運算
提早終止
forward error correction
FEC
Turbo code
Convolutional code
iterative decoding
early termination
ET
Type
thesis
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