Design and Implementation of a Stochastic ARM Core with Circuit Level Recovery Mechanism
Date Issued
2014
Date
2014
Author(s)
Wang, Han-Zhang
Abstract
In this Thesis, we present a new central processor unit (CPU) architecture, which is able to use the whole timing margin and work in a more power efficient way. In advanced process, the process variation is too large to handle. Thus, manufacturers make the slack-time margin larger to ensure the yield rate. On the other hand, Razor cell has been proposed to detect timing error, and recover from it. Considering testability, we need to know the tolerant range voltage as a design factor. However, its error signal detected by Razor is spike-shaped, and could not detect error out of the tolerant voltage range. Thus, we consider the processor with unpredictable behavior as a stochastic processor. For reasons mentioned above, we propose a circuit, Surger, to predict the timing which will cause error, and build a program counter scheduling (PCS) mechanism to recover the core from errors.
In this design, we make the processor more independent with process, voltage, and temperature variations. On the other hand, reliability can be software defined in our Surger architecture. For a design that requires high reliability, we can define a pattern to reach this goal. Similarly, for a design that requires low reliability, we can define a pattern to make it working at a lower supply voltage. By this way, we trade off the reliability of a design with its power consumption, and make the design a better-than-worst-case design.
Subjects
隨機處理器
錯誤回復
錯誤偵測
Type
thesis
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