A Technique of In-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers

A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 700~1300 MHz fractional-N PLL fabricated in a 0.18-μm CMOS process with a 1.17 mm x 1.20 mm die area. The experimental results demonstrate that the integrated rms jitter (10 kHz to 10 MHz) in the fractional-N PLL can be greatly improved from 26.45 ps to 3.91 ps when frequency is ~800MHz. This fully-integrated PLL dissipates 23.5 mA from a 1.8-V supply.