Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors
Journal
2014 IEEE International Nanoelectronics Conference
Date Issued
2016
Author(s)
Abstract
To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.
Type
conference paper