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College of Electrical Engineering and Computer Science / 電機資訊學院
Computer Science and Information Engineering / 資訊工程學系
Hardware-accelerated cache simulation for multicore by FPGA
Details
Hardware-accelerated cache simulation for multicore by FPGA
Journal
Proceedings of the 2018 Research in Adaptive and Convergent Systems, RACS 2018
Pages
231-236
Date Issued
2018
Author(s)
Hung, S.-H.
Ho, Y.-M.
Yeh, C.-W.
Cheng-Yueh, Lee, C.-P.
SHIH-HAO HUNG
DOI
10.1145/3264746.3264766
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/489629
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85056806465&doi=10.1145%2f3264746.3264766&partnerID=40&md5=2082aefc9e510d8a51c44cdde0c2e79f
Type
conference paper