A High-Efficiency and Low-Power Analog-to-Digital Converter
Date Issued
2009
Date
2009
Author(s)
Huang, Yu-Jung
Abstract
This thesis describes a high-speed 6-bit 600MS/s CMOS flash ADC with interpolation. Interpolation technique can reduce the input loading and the number of preamplifier efficiently. This ADC is optimized to operate in high speed application such as ultra-wideband wireless communication network. The analog-to-digital converter consists of a differential track-and-hold circuit, three-stage preamplifiers, comparator array and digital encoder. In order to reduce the transistor random offset error, the outputs of each preamplifier stage are using resistance averaging technique.he designed ADC is fabricated in 0.13μm 1P8M CMOS technology and occupied an area of 1.115x0.633mm2. Measurement result demonstrates that the ADC can achieve a Nyquist rate at 600MS/s with a SNDR above 30dB. The ADC consumes 30 mW from 1.2V power supply.
Subjects
flash ADC
resistance averaging
Type
thesis
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