Design Optimization of Low Voltage/Low Power SoC Microprocessor Circuits via MTCMOS techniques
Date Issued
2014
Date
2014
Author(s)
Hsu, Chien-Po
Abstract
This paper presents a power consumption optimization methodology (PCOM) and a low-power design technique (LPDT) for low-power/ low-voltage microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques.
In Chapter 1, the introduction of the CMOS SoC trends is described, followed by the multi-threshold CMOS (MTCMOS) techniques and the digital circuit design flow.
In Chapter 2, a power consumption optimization methodology (PCOM) for low-power/ low-voltage single-cycle microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques has been presented. Based on the optimization methodology with the dual-threshold techniques, a 32-bit single cycle MIPS microprocessor design has been optimized in terms of circuit design using dual-threshold HVT/SVT CMOS devices. According to SPICE simulation results, the power consumption of the 80,000-transistor 32-bit MIPS microprocessor, using a 90nm CMOS technology and operating at 1V with a 0.9-ns clock period, based on the optimization methodology with the dual- threshold technique, has been reduced by 27.23% during the standby period and 12.53% during the dynamic switching period as compared to the one using the conventional standard- threshold SVT CMOS devices.
In Chapter 3, a low-power design technique (LPDT) for a low-voltage pipelined microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques has been presented. Using the MTCMOS LPDT, a pipelined MIPS microprocessor circuit having 220,000 transistors with 5 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to SPICE simulation results, during the 4-instruction compare operation, this pipelined CPU with the MTCMOS LPDT optimization, designed using a 90nm CMOS technology, operating at 1V and at a 1.3-ns clock period, has been reduced by 40.1% on the leakage power, 17.8% on the average total power and 13.3% on the peak power, as compared to the one using the conventional SVT one.
The substantial saving in leakage power consumption for the pipelined CPU with the MTCMOS LPDT optimization could benefit for hand-held IT applications, where leakage power consumption is the key to battery life.
Subjects
雙重臨界電壓
低功率
微處理器
單晶片系統
Type
thesis
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